1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
2. Description of the Related Art
In semiconductor integrated circuits, particularly an integrated circuit using a MOS transistor, the degree of integration has become increasingly higher. Along with such a high degree of integration, miniaturization of a MOS transistor for highly integrated circuits has been progressed into a nano region. The progress in miniaturization of the MOS transistor involves problems about difficulty in suppressing a leakage current and restriction on reduction in circuit occupancy area due to a need for ensuring a required current amount. With a view to solving this problem, there has been proposed a surrounding gate transistor (SGT) having a structure where a source, a gate and a drain are vertically arranged relative to a substrate, and the gate is formed to surround a columnar (pillar-shaped) semiconductor layer (see, for example, the following Patent Documents 1 to 3).    Patent Document 1: JP 02-071556A    Patent Document 2: JP 02-188966A    Patent Document 3: JP 02-145761A
In the SGT, a channel region is formed to surround a lateral surface of the columnar semiconductor, so that a large gate width is achieved within a small occupancy area. This means that it is required to allow a large ON-current to pass through the small occupancy area. In this case, if resistances of the source and drain are high, the large ON-current will cause difficulty in applying a desired voltage to the source and drain. Therefore, there is a need for an SGT manufacturing method (including a design technique) for reducing the resistances of the source and drain. The large ON-current also gives rise to a need for reducing resistances of contacts.
In a conventional MOS transistor, a gate electrode is formed by depositing a gate material, transferring a gate pattern to a resist on a substrate through lithography to form a mask, and etching the gate material using the mask. That is, in the conventional MOS transistor, a gate length is designed based on the gate pattern. In contrast, in the SGT, the lateral surface of the columnar semiconductor serves as a channel region, and thereby a current flows vertically relative to the substrate. That is, in the SGT, a gate length is designed based on a manufacturing method, instead of based on a gate pattern, so that the gate length and a variation in the gate length are determined by the manufacturing method.
In the SGT, it is required to reduce a diameter of the columnar semiconductor in order to suppress an increase in leakage current along with the miniaturization. In addition, it is necessary to establish a manufacturing method capable of optimizing the source and drain to restrain a short channel effect so as to suppress a leakage current.
Further, in the SGT, it is necessary to reduce a parasitic capacitance in order to minimize power consumption. Thus, there is a need for a manufacturing method capable of reducing a parasitic capacitance.
As with the conventional MOS transistor, the SGT has a need for reducing a manufacturing cost thereof. For this purpose, it is necessary to reduce the number of steps in a manufacturing process.